module spi_send_n (
    input  sys_clk,
    input  sys_rst_n,
    input  miso,
    output cs,
    output sck,
    output mosi
);

  reg [7:0] cnt;
  reg [31:0] test_data;
  reg start_transfer;

  wire [7:0] tx_byte;
  wire tx_dv;
  wire tx_ready;
  wire rx_dv;
  wire [7:0] rx_byte;

  always @(posedge sys_clk or negedge sys_rst_n) begin
    if (~sys_rst_n) begin
      cnt <= 'd0;
    end else if (cnt < 200) begin
      cnt <= cnt + 1'b1;
    end
  end

  always @(posedge sys_clk or negedge sys_rst_n) begin
    if (~sys_rst_n) begin
      start_transfer <= 'b0;
    end else if (cnt == 100) begin
      start_transfer <= 'b1;
    end else begin
      start_transfer <= 'b0;
    end
  end

  always @(posedge sys_clk or negedge sys_rst_n) begin
    if (~sys_rst_n) begin
      test_data <= 32'h01B1F1A0;
    end
  end


  // DUT实例
  SPI_4Byte_Transmitter dut (
      .i_Clk(sys_clk),
      .i_Rst_L(sys_rst_n),
      .i_Start(start_transfer),
      .o_Busy(busy),
      .o_Done(done),
      .i_Data_32bit(test_data),
      .o_TX_Byte(tx_byte),
      .o_TX_DV(tx_dv),
      .i_TX_Ready(tx_ready),
      .i_RX_DV(rx_dv),
      .i_RX_Byte(rx_byte),
      .o_SPI_CS(cs)
  );

  // SPI Master模型实例
  SPI_Master #(
      .SPI_MODE(1),
      .CLKS_PER_HALF_BIT(9)
  ) spi_master_model (
      .i_Rst_L(sys_rst_n),
      .i_Clk(sys_clk),
      .i_TX_Byte(tx_byte),
      .i_TX_DV(tx_dv),
      .o_TX_Ready(tx_ready),
      .o_RX_DV(rx_dv),
      .o_RX_Byte(rx_byte),
      .o_SPI_Clk(sck),
      .i_SPI_MISO(miso),
      .o_SPI_MOSI(mosi)
  );

endmodule

